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high efficiency , eight - string , white led driver for lcd backlight applications data sheet ADD5201 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. tradem arks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features white led driver based on inductive boost converter integrated 50 v mosfet with 2.9 a peak current limit input voltage range: 6 v to 21 v maximum output adjustable up to 45 v 350 khz to 1 mhz adjustable operating frequency built - in soft start for boost converter drives up to eight led current sources led current adjustable up to 30 ma for each channel headroom control to maximize efficiency adjustable output dimming frequency: 200 hz to 10 khz led open/short fault protection selectable brightness c ontrol interface modes pwm input smbus serial interface selectable dimming controls fixed delay pwm dimming control with 8 - bit resolution no delay pwm dimming control with 8 - bit resolution phase shift pwm dimming control with 8 - bit resolution direct pwm dimming control dc current dimming mode with 8 - bit resolution general thermal shutdown under voltage lockout 28 -l ead, 4 mm 4 mm lfcsp applications notebook pc s , umpc s, and monitor display s block diagram step-up switching regul at or eight current sources inter f ace 8-bit dimming contro l logic unde rvo lt age lockout soft s t art therma l protection o vervo lt age protection au t odisable for led open/short 08002-001 figure 1. gener al description the ADD5201 is a white led driver for backlight applications based on high efficiency , current mode , step - up converter tech - nology. it is designed with a 0.15 , 2.9 a internal switch and a pin adjustable operating frequency between 350 khz and 1 mhz. the ADD5201 contains eight regulated current sources for uniform brightness intensity. each current source can be driven up to 30 ma. the ADD5201 drives up to eight parallel strings of multiple serie s connected leds with a 1.5% current regulation accuracy. the device provides an adjustable led driving current up to 30 ma for each channel by an external re sistor. the ADD5201 pro vides various brightness control methods. the led dimming control can be achieved through smbus and/or pulse - width modulation ( pwm ) input. each dimming mode is selectable with two extern al dimming mode selection pins. the device pro - vides a pin adjustable output dimming frequency range from 200 hz to 10 khz. the ADD5201 operates over an input voltage range of 6 v to 21 v, but the device can function with a voltage as low as 5.4 v. the ADD5201 has multiple safety protection features to prevent damage during fault conditions. if any led is open or short, the device automatically disables the faulty current regulator. the internal soft start preve nts inrush current during start up. a thermal shutdown protection prevents thermal damage. the ADD5201 is available in a low profile, thermally enhanced , 4 mm 4 mm 0.75 mm, 28 - lead, rohs compliant lead frame chip scale package ( lfcsp ) and is specified over the industrial temperature range of ? 25 c to +85c.
ADD5201 data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 block diagram .................................................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 step - up switching regulator specifications ............................. 4 led current regulation specifications .................................... 4 smbu s specifications ................................................................... 5 general specifications ................................................................. 5 a bsolute m aximum r atings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 10 current mode, step - up switching regulator o peration ..... 10 internal 3.3 v regulator ............................................................ 10 boost converter switching frequency .................................... 10 dimming frequency (f pwm ) adjustment ................................. 10 current source ............................................................................ 10 backlight brightness control .................................................... 11 pwm dimming mode .............................................................. 11 dc current dimming mode .................................................... 12 safety features ............................................................................ 12 smbus interface .......................................................................... 13 smbus register description ..................................................... 14 external component selection guide ..................................... 16 layout guidelines ....................................................................... 17 typical application circuits ......................................................... 18 outline di mensions ....................................................................... 20 ordering guide ............................................................................... 20 revision history 4 / 12 revision a : initial version
data sheet ADD5201 rev. a | page 3 of 20 functional block dia gram ADD5201 vin vddio shdn nc ov p linear regul a t or volt age reference shutdown error am p uv p com p pwm com p uv p ref gm ll ref ref light load max dut y cycle headroom contro l 8-bit dac current source 1 current source 2 current source 3 current source 4 current source 5 current source 6 current source 7 current source 8 fb8 fb7 fb6 fb5 fb4 fb3 fb2 fb1 iset com p agnd pwm oscill a t or pwm input dut y extrac t or dimming mode selection smbus inter f ace r sense soft s t art current sense osc led open/short f au l t detec t or dref tsd f au l t oc p f au l t oc p ref ov p ref therma l shutdown r s q tsd f au l t oc p f au l t id register f au l t/s ta tus register device contro l register brightness contro l register sw sw fslct pgnd pgnd sda scl sel1 sel2 pwmi c_fpwm r_fpwm current source controller (pwm/analog) 26 4 25 16 22 23 24 27 20 21 5 6 2 3 1 19 18 11 15 14 13 12 10 9 8 7 17 28 08002-003 + + figure 2. functional bloc k diagram
ADD5201 data sheet rev. a | page 4 of 20 specifications v in = 12 v, shdn = high , t a = ? 25 c to +85 c, unless otherwise noted. typical values are at t a = +25 c. step - up switching regulator specifications table 1. parameter symbol test condi tions /comments min typ max unit supply input voltage range v in 6 21 v boost output output voltage v out 45 v switch on resistance r ds(on) v in = 12 v, i sw = 100 ma 150 210 m leakage current i lkg 44 70 a peak current limit 1 i cl 2.9 3.4 4.0 a oscillator switching frequency f sw r f = 150 k 820 1000 1180 khz f sw r f = 470 k 350 khz maximum duty cycle d max r f = 470 k 85 90 % soft start time t ss 1.5 ms overvoltage protection overvoltage threshold on ov p pin rising v ovpr 1.17 1.20 1.24 v falling v ovpf 1.08 1.12 1.16 v allowable ovp level 2 v ovp 47. 7 v 1 test without ramp compensation; the current limit is guaranteed by design and/or correlation to stat ic test. the c urrent limit is dependent on the duty cycle. 2 a maximum 1% deviation of r 2/ r 1 for the ovp setting is considered . the a llow able ovp l evel must not exceed the sw absolute maximum rat ing of 50 v when considering the ovp setting for the deviatio n of the resistors and the ADD5201 v ovp r deviation. see figure 22 for more information. )( v2.1 r2r1 r1 v ovp += led current regulati on specifications table 2. parameter symbol test conditions /comments m in typ max unit current source iset pin voltage v set 6 v v in 21 v 1.16 1.2 1.24 v adjustable led current 1 i led 0 30 ma constant current sink of 20 ma 2 i led20 r set = 141.56 k 19.4 20 20.6 ma headroom voltage of 20 ma v hr20 r set = 141.56 k 0.65 0.85 v current matching between strings 2 r set = 141.56 k ?1.5 +1.5 % led current accuracy 2 r set = 141.56 k ?3 +3 % current source leakage current 1 a f pwm generator dimming frequency range f pwm 6 v v in 21 v 200 10, 000 hz dimming frequency r fpwm = 50 k , c fpwm = 150 pf 820 1000 1180 hz led fault detection open fault delay 1 t d_openfault 6.5 s 1 g uaranteed by design . 2 test at t a = + 25 c.
data sheet ADD5201 rev. a | page 5 of 20 smb us specifications table 3. parameter 1 symbol min typ max unit smbus interface data, clock input low level v il 0.5 v data, clock input high level v ih 2.2 5.5 v data, clock output low level v ol 0.8 v smbus timing specifications clock frequency f smb 10 100 khz bus - free time between stop and start condition s t buf 4.7 s hold time after start condition 2 t hd; sta 4.0 s setup time repeated start condition t su; sta 4.7 s stop condition t su; sto 4.0 s data t su; dat 250 n s data hold time t hd; dat 300 n s clock period low t low 4.7 s high t high 4.0 50 s clock/data fall time t f 300 ns rise time t r 1 s 1 these specifications are guaranteed by design . 2 after this period, the first clock is generated . general specificatio ns table 4. parameter symbol test conditions /comments min typ max unit supply input voltage range v in 6 21 v quiescent current i q 6 v v in 21 v, shdn = high 2.5 5.0 ma shutdown supply current i sd 6 v v in 21 v, shdn = low 40 160 a vddio regulator regulated output v vddio _reg 6 v v in 21 v 3.2 3.3 3.4 v short - circuit current i vddio _sc 6 v v in 21 v 2.3 5.0 ma pwm input voltage high v pwm_high 2.2 5.5 v low v pwm_low 0.8 v allowable input range 200 10, 000 hz thermal shutdown threshold 1 t sd 160 c hys teresis 1 t sdhys 30 c uvlo v in threshold falling v uvlo f v in fall ing 4.4 4.6 v rising v uvlo r v in rising 5.0 5.4 v shdn control input voltage low v il 1.0 v high v ih 2 .0 v input current i shdn shdn = 3.3 v 6 a 1 this specification is guaranteed by design.
ADD5201 data sheet rev. a | page 6 of 20 a bsolute m aximum r atings t a = 25c, unless otherwise noted. table 5 . parameter rating vin ?0.3 v to +2 3 v sw ?0.3 v to +50 v shdn ?0.3 v to +6 v iset, fslct, comp, r_fpwm, c_fpwm ?0.3 v to +3.5 v sda, scl , pwmi ?0.3 v to +6 v fb1, fb2, fb3, fb4, fb5, fb6, fb7, fb8 ?0.3 v to +50 v ovp ?0.3 v to +3 v v ddio ?0.3 v to +3. 7 v sel1, sel2 ?0.3 v to +6 v maximum junction temperature (t j max) 150 c operating temperature range (t a ) ? 25 c to +85 c storage temperature range (t s ) ?6 5 c to +150 c reflow peak temperature (20 sec to 40 sec) 260 c stresses above those listed und er absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 6 . thermal resistance package type ja jc unit 28- lead lfcsp 32.6 1.4 c/w esd caution
data sheet ADD5201 rev. a | page 7 of 20 pin co nfiguration and func tion descriptions 1 pwmi 2 sel1 3 sel2 4 vddio 5 sda 6 scl 7 fb1 17 iset 18 r_fpwm 19 c_fpwm 20 pgnd 21 pgnd notes 1. nc = no connect. 2. connect the exposed paddle to gnd. 16 nc 15 fb8 8 fb2 9 fb3 10 fb4 1 1 agnd 12 fb5 13 fb6 14 fb7 24 sw 25 shdn 26 vin 27 fslct 28 comp 23 sw 22 ovp 08002-002 ADD5201 top view (not to scale) figure 3. pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 pwmi pwm signal input. a 500 k resistor is connected internally between this pin and agnd . 2 sel1 dimming mode selection 1. 3 sel2 dimming mode selection 2. 4 vddio internal linear regulator output. this regulator provides power to the ADD5201 . 5 sda serial data input/output. 6 scl serial clock. 7 fb1 regulated current sink. 8 fb2 regulated current sink. 9 fb3 regulated current sink. 10 fb4 regulated current sink. 11 agnd analog ground. 12 fb5 regulated current sink. 13 fb6 regulated current sink. 14 fb7 regulated cur rent sink. 15 fb8 regulated current sink. 16 nc no connect. this pin remains unconnected. 17 iset full - scale led current setting . a resistor from this pin to ground sets the maximum led current. 18 r_fpwm dimming frequency adjustment with an external r esistor. 19 c_fpwm dimming frequency adjustment with an external capacitor. 20 pgnd power ground. 21 pgnd power ground. 22 ovp overv oltage protection. 23 sw drain connection of the internal power fet. 24 sw drain connection of the internal power fet. 25 shdn shutdown control for p w m input operation mode. active low. this pin can be left open for smbus operation mode. 26 vin supply input . 27 fslct frequency select. a resistor from this pin to ground sets the boost switching freque ncy from 350 khz to 1 mhz. 28 comp compens ation for the boost converter. the c apacitors and the resistor are connected in series between agnd and this pin for stable operation. ep exposed paddle. connect the exposed paddle to ground
ADD5201 data sheet rev. a | page 8 of 20 typical performance characteristics 94 92 90 88 86 84 82 80 78 5 10 15 20 25 input voltage (v) boost converter efficiency (%) 08002-004 8 parallel 8 series 8 parallel 10 series i led = 20ma brightness = 100% f sw = 600khz figure 4. boost converter efficiency vs. input voltage 32 30 28 26 24 22 20 18 16 14 10 12 8 85 105 125 145 165 185 205 225 245 265 r set (k?) led current (ma) 08002-005 figure 5. led current vs. r set 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 pwmi duty cycle (%) led current (ma) 08002-007 figure 6. led current vs. pwm input duty cycle 25 20 15 10 5 0 5 10 15 20 input voltage (v) led current (ma) 08002-008 figure 7. led current vs. input voltage (i led = 20 ma) 32 30 28 26 24 22 20 18 16 14 10 12 8 0.45 0.55 0.65 0.75 0.85 0.95 v hr (k?) led current (ma) 08002-006 figure 8. led current vs. headroom voltage 08002-013 4ms/div 0v 0v 0a v out 10v/div v sw 20v/div i l 1a/div brightness = 100% figure 9. start - up waveforms (brightness = 100%)
data sheet ADD5201 rev. a | page 9 of 20 08002-009 1s/div 0v 0a v sw 10v/div i l 500ma/div v in = 7 v , f sw = 600khz brightness = 100% leds = 10 series 8 p aralle l figure 10 . switching waveforms , v in = 7 v 08002-011 2ms/div 0v 0v 0a v out 10v/div v fb1 5v/div i fb1 20ma/div 3 leds short on fb1 brightness = 100% figure 11 . short - circuit protection waveforms 08002-014 40s/div 0v 0v 0a pwmi 2v/div i fb1 10ma/div v fb1 5v/div f pwm = 10khz brightness = 3% pwmi = 5khz figure 12 . led current waveforms 08002-012 1s/div 0v 0a v sw 10v/div i l 200ma/div v in = 21 v , f sw = 600khz, brightness = 100% leds = 10 series 8 p aralle l figure 13 . switching waveforms , v in = 21 v 08002-010 1ms/div 0v 0v 0v 0a v out 10v/div v fb2 5v/div v fb1 5v/div i fb1 10ma/div led open on fb1 brightness = 100% figur e 14 . open load protection waveforms
ADD5201 data sheet rev. a | page 10 of 20 theory of operation current mode , step - up switching regulator operation the ADD5201 uses a current mode pwm boost regulator to provide the min imal voltage needed to enable the led string to drive at the prog rammed led current. the current mode regu - lation system allows fast transient respons e while maintaining a stable output voltage. by selecting the proper resistor - capacitor network from comp t o a gnd , the regulator response can be optimized for a wide range of input voltages, output voltages, and load conditions. the ADD5201 can provide a 45 v maximum output voltage and drive up to 13 leds (3.4 v/3 0 ma type of leds) for each channel. internal 3.3 v regulator the ADD5201 contains a 3.3 v line a r regulator. the regulator is used for biasing internal circuitry and the voltage levels of the sda and scl pin s . the internal regulator requires a 1 f bypass capacitor. place this bypass capacitor between pin vddio (pin 4) and a gnd , as close as possible to pin vddio . boost converter swit ching frequency the ADD5201 boost converter switching frequency is a djustable , from 350 khz to 1 mhz , by using an external resistor. a frequency of 350 khz is recommended to optimize the regulator for high efficiency , and a frequency of 1 mhz is recommended for small external components. see figure 15 for considerations when selecting a switching frequency and an adjustment resistor (r f ). 1100 1000 900 800 700 600 500 400 300 120 170 220 270 320 370 420 470 r f (k?) switching frequency (khz) 08002-015 figure 15 . switching frequency vs. r f dimming frequency ( f pwm ) adjustment the ADD5201 c ontains an internal oscillator to generate the pwm dimming signal for led brightness control. the led dimming frequency ( f pwm ) is adjustable in the f pwm range of 200 hz to 10 khz by using an external resistor (r fpwm ) and an external capacitor (c fpwm ). for all applications, maintain the r fpwm range w it hin 13 k to 110 k, and maintain the c fpwm range within 20 pf to 390 pf. to reduce the output ripple , it is strongly recommend ed to cho ose an f pwm greater than 5 khz. table 8 . r fpwm and c fpwm recommendations led dimming frequency ( f pwm ) r f pwm (k?) c fpwm (pf) 200 hz 110 390 500 hz 75 200 1 khz 50 150 5 khz 18 47 10 khz 13 20 current source the ADD5201 contains eight current sources to provide accurate current sink ing for each led string. string - to - string tolerance is kept within 1.5% at 20 ma. each led string current is adjusted by an external resistor in the led current range of 0 ma to 30 ma. the ADD5201 contains an led open/short protecti on circuit for each channel. if the headroom voltage (v hr ) of each current source rises above 7.3 v during operation , the current source is disabled in the steady state condition. with the same condition s , if the headroom voltage of the current source rema ins below 200 mv while the boost converter output reaches the ovp level, the ADD5201 recognizes that the current source ha s an open load fault for the current source , and th e current source is disabled. for al l pwm dimming operations, connect the led strings in numerical order, starting with fb1. tie a ny unused current to a gnd. for example, if an application requires four led strings, connect each led string using fb1 to fb4. tie u nused fb pins (fb5 to fb8) to a gnd. programming the led current as shown in the figure 2 , the ADD5201 has an led current set pin (iset) . a resistor ( r set ) from this pin to ground adjusts the maximum led current for f pwm high in the led current range of 0 ma to 30 ma ( see figure 16) . the m aximum led current level can be set using the following equation: (a) 2831 set max led r i pwmi dut y = 80% dut y = 60% dut y = 40% dut y = 20% i led max 0a i led 08002-016 figure 16 . maximum current setting for the led strings
data sheet ADD5201 rev. a | page 11 of 20 backlight brightness control the ADD5201 mode of operation is selectable between the smbus serial input and/or external pwm input. the led brightness control method follow s the method for select ing the mode of operation. for correct operation of the ADD5201 , set the sel1 and sel2 mode selection pins based on the application condi tions ( see table 9 ) . table 9 . brightness control mode selection mode selection settings dimming mode interface sel1 sel2 high high fixed delay pwm smbus high open phase shift pwm smbus high low no delay pwm smbus open high fixed delay pwm pwmi open open phase shi ft pwm pwmi open low no delay pwm pwmi low high dc current smbus low open dc current pwmi low low direct pwm pwmi pwm dimming mode the f pwm duty is internally generated by 256 steps through the pwm input duty and/or the smbus register setting value in the f pwm duty range of 0% to 100%. nevertheless, each current source has a minimum on time requirement for the led current regu - lation such that the dimming is in the range of 3% to 100% when f pwm is 5 khz and when the boost converter switching frequenc y is in the range of 1 m h z to 600 khz. in addition, the brightness controllable range is from 5% to 100% when the boost converter switching frequency is in the range of 350 khz to 600 khz. note that the add520 1 has immunity when the pwm input duty cycle is converted to 256 steps even when the pwm input has 0.195% jitter. fixed delay pwm fixed delay pwm mode is selected when sel1 = open and sel2 = high for a pwmi application, or when sel1 = high and sel2 = high for an smbus application. in fixed delay pwm mode, each current source has a fixed time delay from when the current source turns on and off with respect to the preceding current source. the fixed delay time is set by f pwm . each channel delay ti me is set by the following equation: 256 2 fpwm d t t = w here t fpwm = 1/ f pwm , and f pwm is the led dimming frequency. pwmi f pwm i led 1 i led 2 i led 8 duty = 60% 7 t d t fpwm (duty = 60%) t off t on t d 08002-017 figure 17 . fixed delay pwm dimming timing phase shift pwm the p hase shift pwm mode is selected when sel1 = open and sel2 = open for a pwmi application, or when sel1 = high and sel2 = open for an smbus application. in th e phase shift pwm mode, each current source phase delay is programmed by the number of current sources in operation and the f pwm cycle. each current sour ce delay time is calcu lated by the following equation: n t t fpwm d = where: n is the numbe r of operating current sources. t fpwm is the f pwm cycle. pwmi f pwm i led 1 i led 2 i led 3 i led 4 i led 5 i led 6 i led 7 i led 8 t d t d t d t d t d t d t d t d t off t on duty = 75% t fpwm (duty = 75%) 08002-018 figure 18 . phase shift pwm dimming timing no delay pwm the n o delay pw m mode is selected when sel1 = open and sel2 = low for a pwmi application, or when sel1 = high and sel2 = low for an smbus application. in th e no delay pwm mode, a ll operating current sources turn on and off at the same time without any phase delay.
ADD5201 data sheet rev. a | page 12 of 20 pwmi f pwm i led 1 i led 2 i led 8 t off t on duty = 60% duty = 60% 08002-019 figu re 19 . no delay pwm dimming timing direct pwm the d irect pwm mode is selected when sel1 = low and sel2 = low. in th e direct pwm mode, the pwm input controls the led dimming logic of the ADD5201 . it turns the current sources on and off without any modulation of the pwm input . in addition, each current source has no phase delay in this mode. the led brightness is changed by the pwm input duty ratio. pwmi i led 1 i led 2 i led 3 i led 8 duty = 60% duty = 60% 08002-020 figure 20 . d irect pwm dimming timing dc current dimming m ode dc current mode is selected when sel1 = low and sel2 = open for a pwmi application, or when sel1 = low and sel2 = high for an smbus application. in th e dc current dimming mode, the maximum led current is set by the value of r set . the pwm input or the smbus can change the led current in 256 steps between 0 ma and th e maximum led current. pwmi i led max i led 0a duty = 80% duty = 60% duty = 40% duty = 20% 0.8 i led max 0.6 i led max 0.4 i led max 0.2 i led max 08002-021 figure 21 . dc current dimming safety features the ADD5201 contains many safety featur es to provide stable operation: soft start, overvoltage protection, open load protection , short - circuit protection, undervoltage lockout, and thermal protection. soft start the ADD5201 contains an internal soft start function to prevent inrush current at start up. the soft start time is typically 1.5 ms. overv oltage protection (ovp) the ADD5201 contains ovp circuits to prevent boost converter damage if the output voltage becomes excessive for any reason. to keep a safe output level, the integrated ovp circuit monitors the output voltage. when the ovp pin voltage is reached by the ovp rising threshold, the boost converter stop s s witching, causi ng the output voltage to drop. when the ovp pin voltage becomes lower tha n the ovp falling threshold , the boost converter resumes switching , causing the output to rise. there is about 7.5% hysteresis between the rising and falling threshold s. the ovp level can be calculated using the following equation : ) ( v 2 . 1 r2 r1 r1 v ovp + = ov p com p ref v ov p 22 r1 c1 r2 driver 08002-022 figure 22 . overv oltage protection circuit in general, the suitable ovp level is 5 v higher than the nominal boost switching regulator outpu t. large resistors, up to 1 m ? , can be used for resistor r2 to minimize power loss. in addition, some application s require c1 to prevent noise interference at the ovp pin in the range of 10 pf to 30 p f. open load protection (olp) the add5 201 contains a dynamic headroom control circuit to minimize power loss at each current source. therefore, the min - imum feedback voltage is the reference for regulating the output voltage of the ADD5201 boost converter. if one or more led strings is opened during normal operation, the current source headroom voltage ( v hr ) is pulled to a gnd. in this condition, olp is active if v hr is less than 200 mv until the boost converter output voltage rises to equal the ov p level. short - circuit protection (scp) the ADD5201 contains a short - circuit protection (scp) circuit. if several leds are shorted in an led string, a mismatched voltage is developed across the string. when th e v hr is higher than 7. 3 v, the scp circuit is activated and the current source is disabled. this protection starts to monitor each current source after the startup of the boost converter .
data sheet ADD5201 rev. a | page 13 of 20 underv oltage lockout (uvlo) a uvlo circuit is included with built - i n hysteresis. the ADD5201 turns on when v in rises above 5 .0 v and shuts down when v in falls below 4.6 v. thermal protection thermal overload protection prevents excessive power dissipation from overheating th e ADD5201 . when the junction temperature (t j ) exceeds 160c, a thermal sensor immediately activates the fault protection, which shuts down the device, allowing the ic to cool. the device self starts when the j unction temperature (t j ) of the die falls below 130c. smb us interface when in smbus mode, the ADD5201 can be controll ed with an smb us serial interface. select the smbus mode by using the sel1 and sel2 mode s election pins . read byte as shown in figure 24 , the read byte protocol is four byte s long and starts with the slave address followed by the comm a nd code, which translates to the register index. next, the bus dir ection turns aroun d with the re broadcast of the slave address , with bit 0 indicating a read cycle. the fourth byte contains the data being returned by the backlight controller. the byte value in the data byte should reflect the value of the reg ister being queried at the com ma nd code index. note the bus directions ( shaded in figure 24 ); these are used on cycles where the slaved backlight controller drives the data line. the host master drives a ll of the other cycles . write byte the write byte protoco l is only three bytes long. the first byte starts with the slave address followed by the command code, which translates to the register index being written. the third byte contains the data byte that must be written int o the register selected by the comman d code . n ote the bus directions ( shaded in figure 25 ); these are us ed on cycles where the slaved backlight controller drives the data line . the host master drives a ll of the other cycles. slave device address as shown in figure 26 , the ADD5201 address consists of seven address bits plus one read/write (r/ w ) bit. if the device is in write mode, the lsb is set to 0 and the slave address byte is 0x58. if the device is in read mode, the lsb is set to 1 and the slave address byte is 0x59. t low t buf t hd;d a t t su;d a t t su;s t a t hd;s t a t high t r t f t su;s t o p s s p v ih v il v ih v il scl sda 08002-023 figure 23 . smbus interface s s p r a a a w sla ve address command code sla ve address dat a byte master t o sl a ve sla ve t o master 08002-024 a figure 24 . read byte protocol s w a a p a sla ve address command code dat a byte 08002-025 master t o sl a ve sla ve t o master figure 25 . write byt e protocol r/w 0 0 1 1 0 1 0 08002-026 figure 26 . slave address definition
ADD5201 data sheet rev. a | page 14 of 20 smb us register description the ADD5201 has four registers to control and monitor brightness, fault status, identifications , and oper ating mode s. those registers are 1 - byte wide and accessible via the smbus read/write byte protocols. bri ghtness control register ( address 0x00) th e brightness control register consists of eight bits, brt7 to brt0 , which are used to control the led brightne ss level in 256 steps. an smbus write byte cycle to this register set s the brightness level when the device is in smbus mode. in addition, a write byte cycle to this register has no effect when the device is in a mode other than smbus mode . note that t he o perating mode is selected by the device control register ( address 0x01) . an smbus read byte cycle to th e brightness control register returns the current brightness level , regardless of the value of pwm_sel. a n smbus setting of 0xff for this register set s the device to the maximum brightness output , and a setting of 0x00 set s the device to the minimum brightness output. this register is both readable and writable for all bits . the default value is 0xff. device control register ( address 0x01) this register h as three bits. two bits control the operation mode of the device, and a single bit controls the backlight on/off state. this register is both readable and writable for bit 0 to bit 2. bit 0, named bl_ctl , i s the on/off control for the output leds. bit 1 an d bit 2, named pwm_sel and pwm_md, respectively, control t he operating mode of the device . when the bl_crt bit is set to 1, the device turns on the backlight within 10 ms after the write cycle. when the bl_crt bit is set to 0, the device turns off the back light immediately. the ADD5201 output operating mode is selected by the combination of bit 1 and bit 2 (see table 10) . table 10. operating modes selected by d evice control register , bit 1 and bit 2 pwm_md pwm_sel mode x 1 1 pwm mode 1 0 smbus mode 0 0 smbus mode with dpst 1 x = do not care. the pwm_md bit selects the manner in which the p wm input is to be interpreted. when this bit is 0, the pwm input reflec ts a percent change in the current brightness ( that is, the intel? display power saving t echnology, or dpst , mode) and shoul d be as follows : dpst brightness = c bt ( pw m ) w here : c bt is the c urrent brightness setting from smbus without influence from the pw m. pwm is the percent duty cycle . the pwm signal starts from 100% when operating in dpst mode. when pwm_md is 1, the pwm input has no effect on the brightness setting , unless the ADD5201 is in pwm mode. in add ition, when operat ing in pwm mode, this bit is a do not care (see table 10 ). the pwm_sel bit determines whether the smbus or pwm input drive s the brightness. the r elationship between these two control bits serve s to specify an ope rating mode for the ADD5201 . the defined modes are listed in table 10 . note that , depending on the settings of some bits, oth er bits have no effect and are do not cares , shown as x in table 10. all reserved bits return to 0 when read , and the bits are ignored when written. this default value of the register is 0x00. table 11. brightness control register (address 0x00) bit map bit 7 (r/ w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) brt7 brt6 brt5 brt4 brt3 brt2 brt1 brt0 table 12. brightness control register (address 0x00) bit descriptions bit no. bit name description 7: 0 brt 256 steps of brightness levels. table 13. device control register (address 0x01) bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) reserved reserved reserved reserved reserved pwm_md pwm_sel bl_c tl table 14. device control register (address 0x01) bit descriptions bit no. bit name description 2 pwm_md pwm mode select. 1 = absolute brightness, 0 = percent change (default). 1 pwm_sel brightness mus select. 1 = pwm pi n, 0 = smbus value (default). 0 bl_ctl backlight on/off. 1= on, 0 = off (default).
data sheet ADD5201 rev. a | page 15 of 20 fault/status register ( address 0x02) this register has six status bits that allow monitoring of the ADD5201 operating state. bi t 0, named fault , is a logical or of all fault codes to simplify error detection. in the operation of the ADD5201 , bit 1, named thrm_shdn, is set to 1 when a thermal shutdown event occurs. bit 3, name d bl_stat, is the backlight status indicator. this bit is set to 1 whenever the back - light is on and is set to 0 whenever the backlight is off . bit 4, named 1_ch_sd, is set to 1 when one or more current sources are disabled. in addition, bit 5, named 2_ch_ sd, is set to 1 when two or more current sources are disabled due to an led open/short event during normal operation. all reserved bits return to 0 when read and ignore the bit value when written. all of the bits in this register are read only. the default value for register 0x0 2 is 0x00. identification register ( address 0x03) the id register contains two bit fields to denote the manufac - turer and silicon revision of the ADD5201 . the bit field widths were chose n to allow up to 16 vendors with up to eight silicon revisions each. t o ensure that the number of silicon revisions remains low, the revision field should not be updated until the part is sent to the end customers factory. therefore , if during the enginee ring development process three silicon spins were needed before the device was released to the end customers factory, the next available revision id would be used for these three spins. the manufacture r id of analog devices , inc ., is 6 (bit[6:3] = 0110b). in addition, the initial value of re vx is 0, and subsequent rev x values increment by 1. this register is read only . table 15. fault/status register (address 0x02) bit map bit 7 bit 6 bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) reserved reserved 2_ch_sd 1_ch_sd bl_stat ov_curr thrm_shdn fault table 16. fault/status register (address 0x02) bit descriptions bit no. bit name description 5:4 2_ch_sd, 1_ch_sd the se bits report the number of f aulted strings. 00 = no faults, 01 = one string fault, 11 = two or more strings faulted. 3 bl_stat backlight status. 1 = backlight on, 0 = backlight off. 2 ov_curr input overcurrent. 1= overcurrent condition, 0 = current okay. 1 thrm_shdn therm al shutdown. 1 = thermal fault, 0 = thermal okay. 0 fault fault occurred. logic or of all the fault conditions. table 17. identification register (address 0x03) bit map bit 7 bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) b it 1 (r) bit 0 (r) led panel (bit 7 = 1) mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 table 18. identification register (address 0x03) bit descriptions bit no. bit name description 7 led panel display panel using led backlight, bit 7 = 1. 6:3 mfg[3:0] manufacturer id. (analog devices id is 6.) 2:0 rev[2:0] silicon revision. (revision 0 to revision 7 are allowed for silicon spins.)
ADD5201 data sheet rev. a | page 16 of 20 external component selection guide inductor selection the inductor is an integral part of the step-up converter. it stores energy during the switch-on time and transfers that energy to the output through the output diode during the switch-off time. an inductor in the range of 4.7 h to 22 h is recommended. in general, lower inductance values result in higher saturation current and lower series resistance for a given physical size. however, lower inductance results in higher peak current, which can lead to reduced efficiency and greater input and/or output ripple and noise. peak-to-peak inductor ripple current at close to 30% of the maximum dc input current typically yields an optimal compromise. for determining the inductor ripple current, the input (v in ) and output (v out ) voltages determine the switch duty cycle (d) by the following equation: out in out v vv d ? ? (1) using the duty cycle and switching frequency (f sw ) determines the on time in the following equation: sw on f d t ? (2) the inductor ripple current (i l ) in steady state is l t v i on in l ? ?? solving for the inductance value ( l) , l on in i tv l ? ? ? make sure that the peak inductor current (that is, the maximum input current plus half of the inductor ripple current) is less than the rated saturation current of the inductor. in addition, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. for duty cycles greater than 50% that occur with input voltages greater than half the output voltage, slope compensation is required to maintain stability of the current mode regulator. for stable current mode operation, ensure that the selected inductance is equal to or greater than l min : sw in out min f vv ll ? ? ?? a9.2 inductor manufacturers include coilcraft, inc.; sumida corporation; and toko. input and output capacitors selection the ADD5201 requires input and output bypass capacitors to supply transient currents while maintaining a constant input and output voltage. use a low effective series resistance (esr) 10 f or greater capacitor for the input capacitor to prevent noise at the ADD5201 input. place the input and output capacitors between vin and agnd, as close as possible to the ADD5201 . ceramic capacitors are preferred because of their low esr characteristics. alternatively, use a high value, medium esr capacitor in parallel with a 0.1 f low esr capacitor as close as possible to the ADD5201 . the output capacitor maintains the output voltage and supplies current to the load while the ADD5201 switch is on. the value and characteristics of the output capacitor greatly affect the output voltage ripple and stability of the regulator. use a low esr output capacitor; ceramic dielectric capacitors are preferred. for very low esr capacitors, such as ceramic capacitors, the ripple current due to the capacitance is calculated as follows. because the capacitor discharges during the on time (t on ), the charge removed from the capacitor (q c ) is the load current multiplied by the on time. therefore, the output voltage ripple (v out ) is out on l out c out c ti c q v ? ??? where: c out is the output capacitance. i l is the average inductor current. using the duty cycle and switching frequency (f sw ), users can determine the on time by using equation 2. the input (v in ) and output (v out ) voltages determine the switch duty cycle (d) as shown in equation 1. choose the output capacitor based on the following equation: out out sw in out l out vvf vvi c ??? ? ? ? ) ( capacitor manufacturers include murata manufacturing co., ltd.; avx; sanyo; and taiyo yuden co., ltd. diode selection the output diode conducts the inductor current to the output capacitor and load while the switch is off. for high efficiency, minimize the forward voltage drop of the diode. schottky diodes are recommended. however, to maintain efficiency in high voltage, high temperature applications use an ultrafast junction diode to prevent significant reverse leakage current caused by the schottky diode. the output diode for a boost regulator must be chosen depending on the output voltage and the output current. the diode must be rated for a reverse voltage equal to or greater than the output voltage used. the average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current. using schottky diodes with lower forward voltage drop decreases power dissipation but increases efficiency. the diode must be rated to handle the average output load current. many diode manufacturers derate the current capability of the diode as a function of the duty cycle. verify that the output diode is rated
data sheet ADD5201 rev. a | page 17 of 20 to handle the average output load current with the minimum duty cycle. the minimum duty cycle of the ADD5201 is out in_max out min v v v d ? = where v in_max is the maximum input voltage. for example, d min is 0.5 when v out is 40 v and v in_max is 20 v . schottky diode manufacturers include on semiconductor , diodes incorporated, central semiconductor corp. , and sanyo. loop compensation use of external components to compensate for the regulator loop allows optimizati on of the loop dynamics for a given application. v hr ref r c c c c2 08002-027 g me a figure 27 . compensation components capacitor c2 is chosen to cancel the zero introduced by the output capacitance esr. solving for c2 c out r c esr c2 = for low esr output capacitance, such as with a ceramic capacitor, c2 is optional. for optimal transient performance, r c and c c may need adjust ment after observing the load transient response of the ADD5201 . for most applications , maintain the compensation resistor within a range of 500 to 30 k , and maintain the compensation capacitor within a range of 100 pf to 330 nf . layout guidelines when designing a high frequency, switching, regulated power supply, layout is very importa nt. using a good layout can solve many problems associated with these types of supplies. the main problems are loss of regulation at high output current and/or large input - to - output voltage differentials, excessive noise on the output and switch waveforms, and instability. using the following guidelines can help minimize these problems. make all power (high current) traces as short, direct, and thick as possible. it is good practice on a standard printed circuit board (pcb ) to make the traces an absolute m inimum of 15 mil (0.381 mm) per ampere . keep t he inductor, output capacitors, and output diode as close to each other as possible to reduce the emi radiated by the power traces that is caused by the high switching currents running through them. this also r educes lead inductance and resistance, which in turn reduce noise spikes, ringing, and resistive losses that produce voltage errors. connect t he grounds of the ic, input capacitors, output capacitors , and output diode (if applicable) close together and di rectly to a ground plane. it is also best practice to have a ground plane on both sides of the pcb . this reduces noise by reducing ground - loop errors and by absorbing more of the emi radiated by the inductor. for multilayer boards of more than two layers, use a ground plane to separate the power plane (power traces and com - ponents) and the signal plane (feedback, compensation, and components) for improved performance. on multilayer boards, the use of vias is required to connect traces and different planes. if a trace needs to conduct a significant amount of current from one plane to the other, it is good practice to use one standard via per 200 ma of current. arrange the components so that the switching current loops curl in the same direction. s witching r egulators have two operating power states: one state when t he switch is on and one when the switch is off. during each state, there is a current loop made by the power components that are actively conducting. place the power components so that the current loop is conducting in the same direction during each of the two states. this prevents magnetic field reversal caused by the traces between the two half cycles and reduces radiated emi. layout procedure to achieve high efficiency, good regulation, and stab ility, a good pcb layout is required . use the following general guidelines when designing pcbs: ? place c in close to the vin and agnd leads of the ADD5201 . ? ensure that the high current path from c in (through l1) to the sw and pgnd leads is as short as possible. ? ensure that the high current path from c in (through l1), d1, and c out is as short as possible. ? make high current traces as short and wide as possible. ? keep nodes that are connected to sw away from se nsitive traces , such as comp , to prevent coupling of the traces. if such traces need to be run near each other, place a ground trace between the two as a shield. ? place the compensation components as close as possible to the comp pin. ? place the led curren t setting resistors as close as possible to each pin to prevent noise pickup. ? avoid routing noise sensitive traces near high current traces and components. ? use a thermal pad size of the same dimension s as the exposed pad dle on the bottom of the package. heat sinking when using a surface - mount power ic or external power switches, the pcb can often be used as the heat sink. this is achieved by simply using the copper area of the pcb to transfer heat from the device ; maximizing this area optimize s thermal p erformance.
ADD5201 data sheet rev. a | page 18 of 20 typical application circuits shdn sw sw ov p vin pwmi sda scl vddio sel1 nc sel2 r_fpwm c_fpwm fslct 25 23 24 22 26 1 16 fb1 7 fb2 8 fb3 9 fb4 10 fb5 12 fb6 13 fb7 14 fb8 15 pgnd 20 pgnd 21 agnd iset com p 11 28 17 5 6 4 2 3 18 19 27 nc v in nc c2 0.1f c3 1f c7 30pf c8 4f c5 100nf c6 open c4 20pf c1 2f r2 10k? r3 10k? r9 40k? r8 1.2m? r4 15k? r7 5.6k? r6 150k? r5 470k? r1 10k? l1 10h d1 08002-028 ADD5201 figure 28 . typical application circuits for smbus interface with phase shift pwm dimming mode
data sheet ADD5201 rev. a | page 19 of 20 shdn sw sw ov p vin pwmi sda scl vddio sel1 nc sel2 r_fpwm c_fpwm fslct 25 23 24 22 26 1 16 fb1 7 fb2 8 fb3 9 fb4 10 fb5 12 fb6 13 fb7 14 fb8 15 pgnd 20 pgnd 21 agnd iset com p 11 28 17 5 6 4 2 3 18 19 27 v in nc nc nc nc c2 0.1f c7 30pf c8 4f c5 100nf c6 open c4 20pf c1 2f c3 1f r6 40k? r5 1.2m? r1 15k? r4 5.6k? r3 150k? r2 470k? l1 10h d1 08002-029 ADD5201 on off figure 29 . typical application circuits for pwmi interface with phase shift pwm dimming mode
ADD5201 data sheet rev. a | page 20 of 20 outline dimensions 4.00 bsc sq 112108-a 1 0.40 bsc bot t om view top view 28 8 14 15 21 22 7 exposed pa d pin 1 indic at or 2.70 2.60 sq 2.50 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 pin 1 indic at or 0.25 0.20 0.15 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-wgge. figure 30 . 28 - lead lead frame chip scale package [ lfcsp _wq] 4 mm 4 mm body, very very thin quad (cp - 28 -5) dimensions shown in millimeters ordering guide model 1 temperature ran ge package description package option ADD5201 bcpz -rl ?25c to +85c 28- lea d lfcsp _wq cp -28 -5 1 z = rohs compliant part. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08002 -0- 4/12(a)

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